1. Field of the Invention
The present invention relates to random access memories, and in particular to read sensing arrangements for random access memories.
2. Description of the Related Art
Static random access memories may comprise arrays of memory cells that are each made up of a pair of cross-coupled inverters with a pair of input/output access paths that are connected by way of respective access transistors to a pair of bit lines. The memory cells are arranged in rows and columns, with the memory cells of each column sharing access to a respective pair of bit lines. Except during read or write operations these bit lines are held at a common fixed potential by precharge circuits.
During a read operation, the access paths of any one memory cell of a column are enabled by raising the potential of a respective word line connected to the gate electrodes of the access transistors, whereupon the current/voltage conditions on the respective bit lines start to diverge in a sense dependent upon the data value held in the memory cell, the speed at which they diverge being determined by factors such as the drive from the memory cell and the capacitance of the bit lines. Since typical memory devices incorporate many of these pairs of bit lines the effect on the power consumption can be quite marked.
Known memory designs using voltage sensing techniques take a small bit line differential voltage signal and amplify it over several stages to obtain the necessary data signal levels with a high speed of response, but such techniques have a number of disadvantages, such as the power consumption and the delay involved in effecting the required voltage changes.
There are designs which use current sensing techniques, such as those discussed by Seevink et al. in IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991, pp 525-535, which have the advantage of offering lower power consumption since high capacitance modes such as bit lines and data bus lines do not have to change in voltage. However, these known current sensing arrangements do not provide for effective equalisation of critical nodes to allow a fast response when the current sensing amplifiers are turned on, so that a period of time is generally needed to allow for settling before correct sensing can take place.